1. Field of the Invention
The present invention relates to a phase locked loop circuit (PLL circuit), and more specifically to the structure of the phase lock signal generation unit for the PLL circuit.
2. Description of the Prior Art
A PLL circuit is mounted in, for example, a semiconductor device, and generates from an externally input reference clock signal having a reference frequency an internal clock signal which is synchronous with the reference clock signal and has a frequency at a specific ratio to the reference frequency. When electric power is applied to the PLL circuit, it starts its operation. When the transient period is over, and a predetermined internal clock signal synchronous with a reference clock signal is obtained, a phase synchronous signal (phase lock signal) indicating the situation is issued. Each function block which is provided in a semiconductor device and uses the internal clock signal starts processing signals using the internal clock signal after receipt of the phase lock signal.
FIG. 5 shows the conventional PLL circuit described in the Provisional Publication of the Japanese Patent Application Laid-Open No. 8-316832. The PLL circuit includes an internal clock signal generation unit 31 and a phase lock signal generation unit 38, compares using a phase comparison circuit 32 the phase of an externally input reference clock signal RCLK with the phase of a comparison clock signal VCLK generated by an internal clock signal generation unit 30, and generates a phase lock signal LOCK from a phase lock signal generation unit 38 if the phase difference between the reference clock signal RCLK and the internal clock signal ICLK is within a predetermined range.
In the internal clock signal generation unit 31, an UP output and a DOWN output which are a pair of outputs from the phase comparison circuit 32 are input to a charge pump circuit 33, and control the output potential of the charge pump circuit 33. The output from the charge pump circuit 33 is input to a voltage control oscillator (VCO) 35 through a low pass filter (LPF) 34, and controls the frequency of the internal clock signal ICLK which is an output therefrom. The internal clock signal ICLK is counted by a counter 36 containing a predetermined set value. The count result is fed back to the phase comparator 32 as a comparison clock signal. The set value of the counter 36 is set based on the ratio of the reference frequency to the frequency of the internal clock signal ICLK such that the value of the reference frequency equals the value of the frequency of the comparison clock signal VCLK.
Immediately after the electric power is applied to the PLL circuit, the reference clock signal RCLK is a synchronous with the internal clock signal ICLK, and the PLL circuit starts its operation for synchronization. The phase comparator 32 compares the rise phase RH of the reference clock signal RCLK with the rise phase VH of the comparison clock signal VCLK. If the rise phase RH advances, the output UP and the output DOWN are set to L to increase the output from the charge pump circuit 33, and the frequency of the comparison clock signal VCLK. If the rise phase RH is behind, the output UP and the output DOWN are set to H to lower the output from the charge pump circuit 33 and the frequency of the comparison clock signal VCLK. Thus, a synchronizing operation is performed to make zero phase difference between the signals. When both signals are synchronous with each other, and the phase difference becomes zero, the phase comparator 32 sets the output UP to H, and the output DOWN to L, to fix the output from the charge pump circuit 33 as is. Thus, the clock signals RCLK and VCLK can be synchronous with each other.
In the phase lock signal generation unit 38, when the output UP and the output DOWN of the phase comparator 32 indicate H and L respectively, the output from an AND gate 71 indicates H, and the output passes through a flip-flop circuit 72 having flip-flops FF1 through FF3 serially connected to multiple stages. If the output from the phase comparator 32 enters a stable state and keeps the state for a predetermined period, then the output from all flip-flops FF1 through FF3 is H. Therefore, the output from an AND gate 73 indicates H, and a phase lock signal LOCK is output. Each function lock using the internal clock signal ICLK starts its operation when the phase lock signal is detected.
In the conventional PLL circuit having the above described phase lock signal generation unit, the phase lock signal LOCK is not output until the synchronization between the reference clock signal RCLK and the internal clock signal ICLK continues for a predetermined period as a stable internal clock signal ICLK. The internal clock signal ICLK is often used in an integrated circuit other than the generated integrated circuit. In this case, the internal clock signal has a length covering a plurality of integrated circuits. Such a long clock signal wiring is subject to an influence of the noise from a clock signal wiring, etc. in another system, thereby generating a signal error such as the delayed rise of an internal clock signal. In this case, an asynchronous phase arises only in an output from the phase comparator 32 even though the PLL circuit actually maintains normal synchronization. Such asynchronization can also be caused by the fluctuation of the voltage of power supply.
If an output from the phase comparator becomes asynchronous only for a moment, then the phase lock signal generation unit 38 first releases the phase lock signal LOCK, and then generates again a phase lock signal after stable phase synchronization continues for a predetermined period. During the period, each function block stops its operation and waits for the generation of a phase lock signal even if a stable internal clock signal ICLK has actually been generated. During the function block stop period, the integrated circuit does not proceed with its signal process, thereby lowering the throughput of the signal process.
It is therefore an object to provide a PLL circuit which does not reduce the throughput in the signal process in a function block by avoiding a long stop of the operations of the function block without releasing a phase lock signal as long as the PLL circuit maintains normal synchronization even if a signal error has occurred from noise for a short time in an output from a phase comparator.
The PLL circuit according to the present invention generates an internal clock signal having a frequency at a specific ratio to the reference frequency according to a reference clock signal having the reference frequency, and includes: a phase shift detection unit for comparing at predetermined time intervals the phase of the reference clock signal with the phase of the internal clock signal or a comparison clock signal synchronous with the internal clock signal, for generating a phase matching signal when a comparison result indicates matching, and for generating a phase shift signal when the comparison result indicates non-matching; and a phase lock signal generation means for generating a phase lock signal corresponding to the phase matching signal, and releasing the phase lock signal when the phase shift signal is continuously generated plural times.
Since the PLL circuit according to the present invention does not release a phase lock signal unless the phase shift continuously occurs plural times, the undesired stop in the signal process of a function block can be prevented from being made by simple and small, but not serious noise to the integrated circuit.
It is desired that the phase lock signal generation means generates the phase lock signal when a predetermined time passes after the phase matching signal has been generated. In this case, even if the phase synchronization once occurs after the electric power is applied, the phase synchronization is nullified by a subsequent rebounding, thereby avoiding an undesired operation in the function.
It is desired that the phase shift detection unit detects a plurality of continuous phase shifts according to a plurality of phase shift detection clock signals activated at predetermined time intervals. Thus, an occurrence of a plurality of continuous phase shifts can be detected without fail.
It is desired that the predetermined time intervals are obtained based on the clock cycle of the reference clock signal or the internal clock signal. In this case, a complicated circuit using other clock signals can be avoided.